In recent years, as a next-generation large-capacity memory that substitutes for a conventional NAND type flash memory, there has been vigorously developed a resistance change type nonvolatile memory using a two-terminal element as a memory element like a PCRAM (Phase-change Random Access Memory) or an ReRAM (Resistive Random Access Memory) rather than a three-terminal element like a floating gate type memory element or an MONOS type memory element. Each of these memories stores data by arranging a memory element at an intersection of two independent conductive lines and programming resistance values (e.g., two values of high resistance (OFF) and low resistance (ON)) of the memory element by using a current or a voltage.
For example, in the PCRAM, when the memory element consists of a gallium-antimony-tellurium (GST) compound, a resistance value of the memory element varies depending on a crystalline state and an amorphous state. Further, in the ReRAM, when the memory element is a variable resistance element consisting of, e.g., TiO2, a resistance value of the memory element varies depending on a state that oxygen ions in the variable resistance element move and oxygen defects are thereby continuous between electrodes and a state that the oxygen ions are again arranged in these oxygen defects.
Furthermore, as the ReRAM, one which is of a type whose resistance varies by precipitating a metal filament in a high-resistance layer between electrodes is known. For example, an ReRAM using Cu2S for the high-resistance layer corresponds to this type.
As described above, among the two-terminal elements that store data by utilizing a change in resistance of the memory element, a memory using amorphous silicon for a high-resistance layer reported in Non-patent Literature 1 attracts attention because of its high switching probability or possibility of miniaturization. According to this memory, a metal of an electrode forms a filament in an amorphous layer, and an intensity of resistance caused by this filament exercises a memory function.
In any two-terminal element, multi levels of the memory element must be realized for higher performance.
As a technology that realizes multi levels in each of the two-terminal elements, there is a current compliance control method of controlling a current amount flowing through the memory element to change a resistance value on multi levels when changing the memory level from OFF to ON.
However, in realization of multi levels by the current compliance control method, since current entry and others from a parasitic capacitance produced in the memory element largely affects reliability of the memory element, highly accurately controlling a resistance value of the memory element is difficult.
For example, the parasitic capacitance greatly affects reliability of a set operation (an operation of changing the memory element from ON to OFF), and it has been pointed out that one transistor must be added to one memory element to carry out a highly reliable operation by the current compliance control method.
However, this measure leads to an increase in size of a memory cell (the memory element+the transistor), which results in a cause that obstructs a high capacity of a resistance change type nonvolatile memory.
Therefore, realizing the multi levels in the resistance change type nonvolatile memory that realizes the multi levels by the current compliance control method is very difficult in terms of reliability. For this reason, establishment of a multilevel technology by any other control method than the current compliance control method or suggestion of a configuration of a memory element that realizes such a technology is an issue.